U.S. Pat. No. 4,129,863, to Gray et al., describes a successive approximation, charge redistribution conversion technique commonly used in electronic products today. The technique described in Gray et al. employs an array of binary weighted capacitors that are switched in sequence to divide a reference signal into binary weighted fractions and combine the fractions with a signal to be quantized. A comparator receives the combined signal, compares it against a reference voltage, and produces a serial one-bit data output that, when the conversion is complete, forms a digital word representing the level of the signal to be quantized.
The increased emphasis on low power consumption and mixed-signal CMOS application-specific circuits will result in even more reliance on the Gray et al. circuit technique. However, a drawback to the circuit described in the Gray et al. patent is that the successive approximation conversion algorithm is inherently slow because the comparator determines only one digital bit during each of its decision cycles. Thus, for example, conversion to a 16-bit resolution result requires 16 comparator decision cycles.